1. Technical Field
The present invention relates to equalizers and more particularly to a receiver with a decision feedback equalizer.
2. Description of the Related Art
Terabits-per-second of aggregate bandwidth per integrated circuit is emerging for inter-chip communication in large digital systems. The data is often communicated over widely parallel and bandlimited channels. The two primary challenges for the I/O subsystem is power dissipation and the inter-symbol interference (ISI) due to the limited bandwidth. A number of channel equalization techniques have been introduced to compensate the ISI. Analog or mixed-mode techniques are common for the multi-Gb/s data rates by not requiring very high-speed data converters and by having low complexity. Digitally-tunable discrete-time equalizers have been attractive due to the precise equalization and tunability. In particular, decision-feedback equalizers (DFE) have become popular because of the lower noise and the digital delay chain.
Referring to FIG. 1, a basic structure of a DFE receiver 8 is shown. The architecture uses linear combinations summed by summers 12 of the delayed versions of the decision outputs to cancel the ISI. Since a slicer 10 converts the input signal to binary decisions, the delay chain can be simply implemented by digital flipflops (FF). A DFE also achieves higher signal-to-noise ratio as compared to the linear equalizer because the prior decisions are noise-free, and thus the subtraction of the ISI does not add noise to the equalized signal. Moreover, the tap coefficients (β1, β2, β3) can be adapted conveniently within the receiver 8.
A tight timing constraint exists in the implementation of a mixed-signal DFE. For the first tap β1 of the equalizer, the decision from the data slicer 10 must be fed back to the adder 12 and settle within one bit-time (Tbit). A direct implementation of the DFE structure in FIG. 1 requires high-speed and low-fanout circuits in order to meet the timing requirement.
As the operating frequency (Hz) increases, the power requirement (W) of the data slicer 10 increases rapidly in order to speed up the regeneration time when self-loading is comparable to the load capacitance. Additionally, the analog-summation node can have a large capacitance. Large analog current is often needed to reduce the summation time constants. For a given process technology, the total power of the DFE increases dramatically with higher data rates.
Several techniques have been introduced to relax the critical path delay of equalizers. Because of inherent feedback, time interleaving, a common way of relaxing the timing constraint, does not benefit a DFE.
Referring to FIG. 2, regardless the amount of interleaving, the output of each slicer 10 still has to provide a decision and feedback to the next slicer 10 within 1 bit time (Tbit). Not only is the critical path 15 not relaxed, but interleaving the DEE also results in increased power dissipation since the number of high-speed elements is multiplied.
One common approach to reduce the critical path delay is to use a look-ahead architecture, also referred to as loop-unrolled DFE, partial-response DFE, or speculative DFE. The architecture is illustratively shown in FIG. 3. Instead of feeding back the slicer decision for a first tap, a look-ahead DFE makes two decisions with two slicers 20 where each slicer 20 assumes a previous bit is a 0 and 1. The received data value is selected from these two slicer outputs based on the previous data value with a multiplexer 24. The look-ahead technique is typically limited to only one tap because of an exponential increase in the number of slicers with the number of taps. As a result, the second and higher order taps of the DFE are often fed back directly.
However, the second-tap feedback still results in a timing constraint. Dynamic feedback techniques have been proposed but result in sensitivity to a critical race that is sensitive to process variations. Nevertheless, with a look-ahead 1st tap and a dynamic 2nd tap, the timing constraint of a DEE can be improved by a factor of two when compared to a direct-feedback implementation. It is important to note that any power benefit from relaxing the critical path delay is counterbalanced by the duplicated slicer hardware which proportionally increases the power dissipation.
Recently, look-ahead decision feedback equalization has become more popular due to the look-ahead architecture, which relaxes the stringent timing constraint of a feedback path. However, look-ahead architecture requires hardware redundancy to cover all possible combinations of predicted data. Although only the first tap look-ahead is needed typically, the hardware and thus power doubles for a binary signal. Note that the most power consuming circuits (summers and comparators) have to be duplicated for look-ahead.
Some receivers avoid adding a second tap in first tap look-ahead DFE because the speed improvement over direct DFE is less than twice, but power is double. Therefore, a need exists for an alternative way to relax the critical path in DFEs with minimum additional power.